As a result of our longstanding partnership, customers using Altera devices can take advantage of the new high-reliability features in the Synplify Premier software for use in their mission-critical applications." "The enhanced TMR functionality in Synopsys' Synplify Premier software automatically implements the triplicated logic and associated voting and control mechanisms, providing a complementary solution to our Quartus II software. "Altera's FPGAs provide a proven solution for high-reliability applications," said Alex Grbic, director of software and IP marketing at Altera. The latest Synplify software also defines a migration path from Xilinx's ISE place-and-route flows to Vivado flows by providing constraints translation, constraints editing, review and reporting within the Synplify tool. The new flow adopts standard Synopsys Design Constraints (SDC) timing constraints specifications and provides the option to use the Verilog netlist format as the output from synthesis and input to place-and-route.
Synopsys and Xilinx worked together to provide an integrated RTL-to-gates flow that simplifies the migration path to the Xilinx Vivado Design Suite for designers using Xilinx 7 Series FPGAs. "We have been working closely with Synopsys for over a year to ensure seamless integration between Synplify and the Vivado Design Suite for customers using our 7 series FPGAs," said Tom Feist, senior marketing director of design methodology Xilinx. "In particular, the new constraints setup capability offered in the latest Synplify release has greatly helped our customers accelerate the creation of good design constraints and improve design performance." This ability to determine whether conversion completed as planned saves designers debug time and is particularly useful when initially bringing up a prototype on a board. In addition, enhancements to the clock conversion feature enable users to create custom reports early in the synthesis run and perform TCL script-based searches of the design database to find converted clocks. The erroneous modules can now be exported, fixed in parallel with the main design, and then merged back into the design incrementally. These features, including TCL scripts and clock conversion and error reports, can automatically identify and isolate multiple erroneous modules and interface issues in a single synthesis run. The new hierarchical design error isolation and incremental fix capabilities in the Synplify Premier software, in conjunction with enhanced continue-on-error capability, can significantly shorten design cycles by speeding up design fixes and reducing the number of iterations needed to successfully bring-up the FPGA design on the board. Synplify customers with all-vendor configurations of Synplify Pro and Premier can now target Achronix's Speedster22i HD FPGAs built on Intel's 22nm process technology with 3-D Tri-Gate transistors.
For designers targeting Altera FPGAs, the new version of the Synplify Premier tool provides high reliability capabilities, such as triple modular redundancy (TMR) and automatic inference of error-correcting code (ECC) memories. For engineers targeting Xilinx 7 Series devices, new automated constraints setup assistance and checking for Xilinx's Vivado Design Suite simplifies migration from the Xilinx ISE design software, saving time and enhancing quality of results. The 2012.09 Synplify Premier release also delivers significant enhancements for engineers targeting Altera and Xilinx FPGAs and, for the first time, includes support for Achronix Speedster 22i HD FPGAs. These features enable FPGA designers and engineers deploying FPGA-based prototypes such as Synopsys' HAPS systems to cut weeks off their design project schedules.
The 2012.09 Synplify releases include new multiple error isolation and incremental fix capabilities that accelerate FPGA implementation.
(Nasdaq:SNPS), a global leader accelerating innovation in the design, verification and manufacture of chips and systems, today announced the latest release of the Synopsys Synplify Pro® and Synplify® Premier FPGA synthesis tools.
New Features Include Fast Error Identification, Incremental Fix and Customizable Reporting for Faster FPGA Implementation and Prototype Bring-Up